The present invention generally relates to a memory controller for a flash memory, a memory system having the memory controller, and a method of controlling the flash memory.
In a memory system employing a flash memory, the relationship between logical addresses provided from a host system and physical addresses in the flash memory is typically managed in logical blocks. Each logical block is composed of plural logical sectors. Each logical address is assigned to each logical sector. Each logical block is assigned to a prescribed number of physical blocks (one or more physical blocks), each of which is an erasing unit, in the flash memory. Each physical block is composed of plural physical pages, each of which is a writing unit and also a reading unit.
Data writing to physical pages in a physical block must be executed in ascending order of their page numbers. Therefore, when writing data to a physical block, the physical page having the smallest page number among free physical pages in the physical block is identified, and then data writing is executed from the physical page having the smallest page number in the ascending order.
For example, the relationship between logical blocks and physical blocks is managed on a basis of an address translation table, as shown in Reference 1 (JP-A-2001-243110). Further, according to Reference 1, in view of efficiency of access to the flash memory and management of the address translation tables, the tables are made up in logical zones each composed of plural logical blocks, and some of the tables are hold in a SRAM (Static Random Access Memory).
Also, a physical page having the smallest page number among free physical pages in a physical block is identified in a manner as shown in Reference 2 (JP-A-2007-323138).